Events

The rapid rise of foundation models has significantly increased the computational demands of modern AI systems, exposing the limitations of monolithic system-on-chip designs. Heterogeneous chiplet-based architectures have emerged as a scalable alternative, enabling modularity, improved yield, and higher performance. This talk presents a unified approach to designing such systems through communication-aware chiplet organization, topology optimization using space-filling curves, and integration of compute- and memory-centric units. By co-optimizing architecture, interconnects, devices, and packaging, these frameworks enable improved performance, energy efficiency, and reliability, while highlighting key challenges in building next-generation AI infrastructure.